Sampling as a substrate.
A new class of chip is being built whose transistors draw random samples with their own thermal noise instead of computing them with arithmetic. The physics behind it is a century old and belongs to everyone: the Ising model of 1925, Glauber's update rule of 1963, Gibbs sampling from 1984. This page teaches the loop those chips accelerate, runs it live on your own device, and prices the result against the published figures. The instrument checks itself against an exact 1944 solution before it reports anything, and every number on the page is labelled with what kind of number it is.
1. State what a thermodynamic sampling unit computes, and what it charges for.
2. Run a verified Gibbs sampler on your own GPU and read its throughput honestly.
3. Trace a headline hardware claim back to what was measured, simulated, and projected.
4. Say where the boundary sits today for embodied workloads, and what would move it.
A century of open physics.
An energy-based model scores every configuration of its variables; sampling means drawing configurations with probability set by that score. Gibbs sampling does it one variable at a time: look at your neighbours, compute a local field, flip a biased coin. Colour the graph like a checkerboard and half the variables can update at once, which is exactly the parallelism a GPU exploits in threads and a thermodynamic chip exploits in physics. The chip's promise is that the biased coin comes from transistor noise at femtojoules, where a digital generator pays hundreds of femtojoules in logic. The chip's cost is everything that crosses its edge.
7.09 fJ in the published device model. Label: pre-silicon circuit simulation, vendor's own appendix (arXiv:2608.01615, Table IV).
1.692 pJ, the price of 239 updates. Same source, same label. Reading everything, every step, is already the wrong regime.
153.6 pJ, the price of about 21,700 updates, with reprogramming capped near once per second. The architecture wins where many local updates happen between rare crossings. That sentence is the whole design space.
Run the sampler on your own device.
This is the same loop, written for the GPU in your machine and run at the full published scale of the newest chip design: 269,568 nodes, each coupled to 16 neighbours. Protocol first: the sampler simulates a small magnet and must reproduce Onsager's exact solution for it, a closed-form answer from 1944, before any throughput is reported. If the physics check fails, the instrument refuses to give you a number. Then it measures how many node updates per second your device performs, and prices each one at the wattage of the machine you are holding.
For scale, labelled measured on our machines with the machine otherwise idle: one CPU thread of the same loop in portable Rust does 73 million updates per second, eighteen threads do 380 million, and the laptop GPU this page was built on does 9.35 billion in a browser tab. An earlier figure of 11.6 million per thread was measured while background jobs shared the machine, and is corrected here: a throughput number taken on a busy machine is a measurement of the background jobs. The lattice you watch ordering during verification is the magnet passing its exam.
How to read a hardware claim.
The headline attached to this hardware class is a ten-thousandfold energy advantage over GPUs. Tracing it is a better lesson than believing or dismissing it. The figure comes from a system-level simulation of a proposed chip generating small binarised images, against GPU baselines far below full utilisation. The one silicon-measured item in the record is the noise source itself: a working femtojoule-class probabilistic bit. The vendor's own refined appendix, published days after the headline, prices the full inference pipeline about ten times higher than the coarse model behind it. And the peer-reviewed anchor, measured on real hardware against properly optimised digital samplers, is 5 to 18 times. None of these numbers is the other; a modelled figure, a projected figure and a measured one carry different provenance, and the discipline of this programme is that they are never averaged.
A subthreshold-CMOS probabilistic bit: programmable bias, roughly 100 ns decorrelation, femtojoule-class randomness. That is the complete list to date.
Every machine-learning result in the record: image generation on a software model of the proposed architecture, scored at parity with small GPU baselines.
The energy multipliers, from an analytic model with one of four terms measured, input and output excluded. The refined version is about ten times more expensive than the headline's basis.
5 to 18 times over optimised GPU and TPU samplers, on sparse-graph FPGA probabilistic computers. Aadit et al., Nature Electronics 2022.
We run the whole stack, in the open, on anything.
The Institute's position is that a substrate this promising should be learnable and runnable by anyone, on hardware they already own. So the programme built the full equivalent stack in pure Rust with no dependencies: the sampler, verified against the exact 2D Ising solution to four decimal places; a stochastic-program layer whose three independent gradient estimators agree, and whose trained controller lands on a provably optimal gain; a compiler that fits arbitrary conditional kernels onto the device's own published topology, with its error bound verified exactly; and the browser instrument above. The same code compiles unchanged from CPU to WebAssembly, and the joules ledger travels with it.
We compiled a robot reaching controller onto the published degree-16 fabric. A coherent quantised target exists: the discretised controller still reaches 90 percent of targets. The compiled kernels plateau near 45 percent. What is missing is multiplicative structure: the reaching law multiplies state variables together, and sparse local pairwise couplings with a few hidden spins cannot route those products at this scale. No published work anywhere demonstrates a control workload on this hardware class; this measurement says why, and is labelled: measured, in simulation, on the vendor's published topology.
Two things. Publishing the energy price of clamping an input, which decides whether a 100 Hz control loop is feasible at all under the once-per-second reprogramming cap. And capacity for products, whether through deeper factor chains, more hidden units per die, or a topology designed for conditionals rather than generation. For a robot the prize is bounded either way: below roughly one watt of compute, the arm's motors, not the model, set the energy bill.
The ferrotherm repository cargo add ferrotherm The Energy Lab The EFA programme Work to be done
The library is open source under Apache 2.0, has zero dependencies, and ships its verification suite: every module must reproduce an exact result before it is trusted. AGENTS.md and llms.txt in the repository are written for AI agents; the same code compiles unchanged to WebAssembly.
Sources: Ising, Z. Physik 31 (1925) · Glauber, J. Math. Phys. 4 (1963) · Geman and Geman, IEEE TPAMI (1984) · Onsager, Phys. Rev. 65 (1944) · arXiv:2510.23972 (npj Unconventional Computing 2026) · arXiv:2608.01612 · arXiv:2608.01615 · Aadit et al., Nature Electronics 5 (2022) · Jarzynski and Olano, JCGT 9(3) (2020). Device figures are the vendor's pre-silicon estimates; our measurements are labelled where they appear.