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Reading the Field
85 claims, and how to tell them apart.
A teaching corpus. 85 organisations, laboratories and national programmes are recorded here with what each actually demonstrated and how well that demonstration is evidenced. The table is the lesson: read down the verification column and you are practising the skill this field most requires, which is telling a measured result from a reported one, a reported one from a company statement, and any of them from a press release.
85
entries tracked
17
that learn at inference
41
independently verified
19
national programmes
Verification is recorded per row as verified, reported, self-published or claimed. Letters of intent are never counted as awards.
How to use this
Four questions to bring to any row.
The habit this table is meant to build transfers to any technical literature you will read. Work through a few rows with these questions and the pattern becomes automatic.
Who produced the number, and did anyone else reproduce it?
A result nobody has independently repeated is a hypothesis with good presentation. Note how few rows here clear that bar.
Is the comparison against a fair baseline, or against a weak one?
A hundredfold gain against an unoptimised implementation is a statement about the implementation, not the substrate.
Is the figure measured, modelled, or projected from a component?
These are different kinds of claim. Averaging them together is the most common error in the field, and the hardest to spot after the fact.
Has money been committed, or merely announced?
A letter of intent is not an award. Several rows here would read very differently if that distinction were dropped, which is why it is kept.
An exercise worth doing: pick any five rows, cover the verification column, and predict it from the wording of the claim alone. The gap between your prediction and the record is the thing to study.
The course this supports: PAI-270 →How this map is kept current
Thermodynamic & probabilistic substrates
| Organisation | Region | Approach | Result or claim | Learns live | Verification |
|---|---|---|---|---|---|
| Extropic Startup Prototype -> early access | USA | Thermodynamic sampling units (transistor p-bits, room-temp CMOS) X0 prototype; XTR-0 platform; Z1 production chip (100k+ probabilistic circuits) slated for 2026 early access; Z1.5 planned at a US foundry under the CHIPS project; Denoising Thermodynamic Models (DTM); thrml simulator | DTM simulations: ~10,000x less energy per generated sample vs GPU generative models on binarized Fashion-MNIST (simulation-based projection) | Partial (sampling-native; training off-chip) | Reported / Claimed |
| Normal Computing Startup Tape-out | USA | Stochastic processing units; thermodynamic ASIC; thermodynamic linear algebra CN101 thermodynamic ASIC taped out (2025); Nature Communications prototype (matrix inversion, Gaussian sampling) | Thermodynamic-advantage results for linear algebra & sampling primitives (papers) | Partial | Reported |
| Signaloid Startup Commercial (first probabilistic computing to market) | UK | Distribution-extended (UxHw) probabilistic computing on standard digital CMOS - propagates full probability distributions through programs AWS cloud platform (customers incl. Boeing, CERN); microSD edge module via Mouser; sub-10 W ASIC taped out at TSMC (May 2026) | Commercially deployed uncertainty-tracking compute across cloud, edge module, and ASIC form factors | Partial (uncertainty-native) | Reported |
| Ludwig Computing Startup Development | USA | Probabilistic computing (p-bit lineage; founded by Behtash Behin-Aein, p-bit co-originator) Early-stage probabilistic hardware | Positions thermodynamic computing as new implementation of the probabilistic paradigm | Yes (sampling-native) | Reported |
| Klere Independent / startup FPGA proof-of-mechanism | USA [verify] | Ternary Hopfield settling fabric on FPGA; joule-typed software stack (Joule language, flowg VM, ternaryOS, ternary-fabric); 'EPU' energy-accounting thesis AWS F2 (Virtex UltraScale+) 64x64 settling engine; provenance-tagged energy receipts; CC0 open artifacts | 0.1596 +/- 0.0006 pJ/accumulate measured (frequency-sweep slope; FPGA stand-in for ASIC); 100% pattern recall via settling with 68% of weight memory stuck at zero vs 84% one-shot; 2.12 pJ/recall (modeled) | Yes (settle x2 local learning; Hebbian) | Self-published |
| Vaire Computing Startup Prototype | UK / USA | Reversible / near-adiabatic computing Reversible logic test chips | Roadmap claims of order-of-magnitude energy reduction for target workloads | No | Reported |
| UCSB (Camsari Lab) Academic Lab demos | USA | Probabilistic bits (p-bits); stochastic magnetic tunnel junctions; probabilistic Ising machines MTJ-based p-computers; FPGA p-bit clusters (10^6-scale emulation) | 250-MTJ probabilistic Ising machine with parallel cluster updates ~10x over serial Gibbs (Nat. Commun. 2026, with collaborators) | Yes (sampling-native; hardware Boltzmann learning) | Verified |
| Tohoku University (Fukami / Ohno) Academic Lab demos | Japan | Spintronic stochastic devices for probabilistic computing sMTJ p-bit demonstrations (with UCSB collabs) | Room-temperature nanosecond-scale stochastic MTJs for p-computing | Yes (sampling-native) | Verified |
Ising machines & annealers
| Organisation | Region | Approach | Result or claim | Learns live | Verification |
|---|---|---|---|---|---|
| Toshiba Corporate Commercial | Japan | Simulated Bifurcation Machine (quantum-inspired classical dynamics on FPGA/GPU) SBM cloud + edge; FX arbitrage prototype; 2026 positioning: Ising machines as white-box decision layer for autonomous systems (AGV routing etc.) | Microsecond-latency optimal arbitrage detection across 8-currency combinations; >90% probability of finding most profitable opportunity | No (optimizer; pairs with learned models) | Verified |
| Fujitsu Corporate Commercial | Japan | Digital Annealer (CMOS ASIC); MAQO many-core optimization architecture Digital Annealer generations; cloud service | Competitive large-QUBO benchmark results vs. software SA and quantum annealing | No | Verified |
| Hitachi Corporate Commercial pilots | Japan | CMOS annealing; STATICA fully-parallel annealer STATICA; momentum annealing | Fully-parallel spin updates for dense problems | No | Verified |
| NEC Corporate Commercial | Japan | Vector annealing on SX-Aurora Vector Annealing service | Large-instance QUBO service offerings | No | Reported |
| NTT Corporate Research -> pilot | Japan | Coherent Ising Machine (optical parametric oscillators); IOWN photonics-electronics convergence LASOLV CIM (2,000-spin class); IOWN roadmap | 2,000-spin optical Ising computation; CIM benchmark studies vs annealers | No | Verified |
| D-Wave Public company Commercial | Canada / USA | Quantum annealing Advantage2 system (4,400+ qubit class) | Commercial annealing services; contested but growing application results | No | Verified |
| Oscillator-Ising / sampler academic cluster (multiple groups) Academic Lab demos | USA / EU | Oscillator-based Ising machines reconfigured as probabilistic samplers OIM-as-sampler demonstrations | OIMs shown to operate as samplers rather than pure optimizers (Communications Physics, Feb 2026) | Yes (sampling) | Verified |
Neuromorphic & spiking systems
| Organisation | Region | Approach | Result or claim | Learns live | Verification |
|---|---|---|---|---|---|
| Unconventional AI Startup Development (founded ~2 months before raise) | USA | Brain-inspired neuromorphic + analog computing explicitly targeting the brain's ~20 W efficiency envelope; founded by Naveen Rao (Nervana, Nirvana->Intel, MosaicML->Databricks AI lead) Architecture undisclosed; founded late 2025 | Record capital signal for the paradigm; claims of orders-of-magnitude efficiency vs GPUs are pre-product | Expected (brain-inspired premise) | Reported / Claimed |
| Zhejiang University + Zhejiang Lab Academic + provincial lab Research system (world's largest neuromorphic computer) | China | Darwin 3 spiking chip; brain-inspired OS; online neuromorphic learning instruction set Darwin Monkey ('Wukong'): 960 Darwin 3 chips, 2B+ spiking neurons, 100B+ synapses, ~2 kW; runs a spikified DeepSeek-derived model | Macaque-scale neuron count on ~2,000 W; reasoning / generation / math task demos | Yes (on-chip online learning) | Verified |
| Intel Labs Corporate Research | USA | Loihi 2 neuromorphic processor; Lava framework Hala Point (1.15B neurons, 2024); Loihi 2 research cloud | 1.15B-neuron system; orders-of-magnitude efficiency on sparse event workloads | Yes (programmable plasticity) | Verified |
| IBM Research Corporate Research / prototype | USA | NorthPole (near-memory digital inference); analog PCM in-memory compute (Hermes-class) NorthPole 2023; analog AI chips | NorthPole: large efficiency/latency gains vs GPUs on vision inference; PCM crossbar accuracy milestones | No (NorthPole is inference) | Verified |
| SpiNNcloud (TU Dresden spinout) Startup Commercial research systems | Germany | SpiNNaker2 many-core neuromorphic 5M-core-class SpiNNaker2 systems for research customers | Large-scale event-driven simulation platforms | Yes (plasticity) | Reported |
| BrainChip Public company Commercial (edge) | Australia | Akida event-based neural processor; on-chip learning Akida 2.0 IP + chips | Ultra-low-power event-based inference + incremental learning at the edge | Yes (edge on-chip learning) | Verified |
| SynSense Startup Commercial (edge) | China / Switzerland | Ultra-low-power SNN processors + DVS sensing Speck (sensor+processor); DYNAP line | Sub-mW always-on visual processing | Partial | Reported |
| Innatera Startup Commercial sampling | Netherlands | Analog-mixed-signal spiking MCU Pulsar spiking neural processor | Sub-mW sensory inference | Partial | Reported |
| Peking University + CAS Academic Research | China | Memristor-based neuromorphic in-memory chip for real-time brain modeling 40 nm memristor chip (Science, Jul 2026) | Real-time brain-surface modeling; up to 478x faster than an A100 on that domain-specific workload; 2.12 ms latency | Partial | Verified (domain-specific claim) |
| IISc Bengaluru (molecular neuromorphic) Academic Lab prototypes | India | Molecular-film memristive devices ('Brain on a Chip' lineage): metal-organic films storing/processing in thousands of analog conductance states Molecular memristor platforms with reported 16,500-state precision | Ultra-high-precision analog states in molecular devices - India's most distinctive alternative-compute asset amid a mainstream fab catch-up strategy | Partial | Reported (peer-reviewed lineage) |
| Tsinghua (Tianjic) / Lynxi Academic + startup Research -> commercial | China | Hybrid ANN/SNN neuromorphic architecture Tianjic (Nature 2019 cover); Lynxi commercial chips | Hybrid-paradigm chip demos (autonomous bicycle); commercialized lines | Partial | Verified |
| Cortical Labs Startup Commercial research units | Australia | Synthetic biological intelligence: living human neurons integrated with silicon (DishBrain lineage) CL1 biological computer; neuromorphic/wetware system launched 2026 | Neurons-on-silicon systems learning tasks (e.g., Pong) with intrinsic plasticity | Yes (biological plasticity) | Reported |
| Peking University (Yang Yuchao group) Academic Published research | China | Volatile + non-volatile memristor co-architecture End-to-end memristor hardware system, single-pulse encoding | 38x energy-efficiency gain and 6.4x speed-up reported; two papers, Nature Electronics, Jan 2026 | Partial | Reported (peer-reviewed) |
| Peking University + Chinese Academy of Sciences Academic Published research | China | Phase-change memristor neurodynamic chip Brain-simulation chip; single operation ~2.12 ms | Claimed 50-478x faster than high-end GPU on brain-simulation workloads; published in Science, 2026 | Partial | Reported (peer-reviewed); speed-up range is workload-dependent |
| Beijing Institute of Technology (Sun Linfeng group) Academic Research | China | 2D antiferroelectric CuBiP2Se6 for edge AI Single device through to neuromorphic arrays | Materials-level demonstration; device-to-array progression reported, no system-level energy figure | Partial | Reported; early stage |
| China National S&T Major Project (brain-inspired) National programme Policy target | China | State targets for brain-inspired chips 2026 funding-guide requirements | Requires >=128 TOPS INT8 measured on typical workloads, >=10 TOPS/W, and >=3 multimodal fusion tasks | n/a | Official programme document; a target, not a result |
| IIM信息 (IIM Information) — shipment tracking Industry research Reported figure | China | Category-level shipment tracking across neuromorphic hardware 全球神经形态计算芯片行业发展与展望报告 (29 Apr 2026) | 2025 global neuromorphic chip shipments >48M units, +212% YoY (67% edge, 23% data-centre accelerator). SCOPE CAVEAT: the report states no formal definition and counts event-driven cameras and neuromorphic sensory interfaces alongside SNN processors, so this is NOT comparable to merchant-processor counts (Akida, Loihi). The same publisher's 2026 market size ($7.25B) sits ~20x above Western trackers ($0.34-0.37B for 2025), which is itself evidence the categories differ. | n/a | Reported — single industry-research publisher, methodology not disclosed, not independently replicated |
Photonic & optical computing
| Organisation | Region | Approach | Result or claim | Learns live | Verification |
|---|---|---|---|---|---|
| Neurophos Startup Development -> early deployment | USA (Austin) | Metasurface/metamaterial optical modulators; photonic AI inference for data centers OPU integrating 1M+ micron-scale optical processing elements per chip; 'ExaOPS-class' systems | Claims up to 100x performance and energy efficiency vs conventional accelerators [vendor claim] | No | Reported / Claimed |
| OLIX Computing Startup Development | UK | AI inference chip with integrated optical components; novel memory and interconnect architecture Inference processor (details undisclosed) | Claims photonics outperforming silicon interconnect paths [vendor claim] | No | Reported / Claimed |
| Optalysys Startup Development | UK | Optical computing (Fourier-optical cores; FHE acceleration focus) Optical compute systems | Optical acceleration for encrypted-compute workloads | No | Reported |
| Tsinghua (Fang / Dai groups) Academic Research | China | Diffractive-interferential photonic chiplets; all-analog photoelectronic (ACCEL) Taichi (Science 2024, 160 TOPS/W); Taichi-II (training with light); ACCEL | Taichi-II claimed ~1,000x energy efficiency vs H100 for target workloads (media/vendor claim, hard to verify) | Partial (Taichi-II trains optically) | Verified (Taichi) / Claimed (Taichi-II ratio) |
| Shanghai Jiao Tong Univ. + Tsinghua (LightGen) Academic Research | China | Photonic generative processor LightGen: 2M+ photonic neurons; image / 3D / video generation (Science, Dec 2025) | ~100x speed/efficiency claims vs GPUs on specific generative workloads; explicitly task-specific, not general-purpose | No | Verified (paper) / task-specific |
| SJTU Wuxi photonic pilot fab + CHIPX / Turing Quantum Academic + industrial Pilot production | China | Photonic chip pilot production (incl. thin-film lithium niobate) 6-inch photonic wafer series production (Jun 2025); ~12,000 wafers/yr pilot line | First domestic photonic pilot lines; framed domestically as strategic answer to export controls | n/a | Reported |
| Lightmatter Startup Commercial ramp | USA | Silicon photonics interconnect (Passage); earlier photonic compute (Envise) Passage 3D photonic interposer | Photonic interconnect for AI clusters (energy of data movement) | No | Reported |
| Celestial AI Startup Commercial ramp | USA | Photonic Fabric optical interconnect Photonic Fabric | Optical scale-up fabric for accelerators | No | Reported |
| Lightelligence Startup Prototype | USA / China | Photonic computing & interconnect PACE optical compute engine; oNET | Photonic Ising/optimization demos | No | Reported |
| Q.ANT Startup Prototype / early commercial | Germany | Photonic native processor (TFLN) Photonic NPU for AI & HPC | Analog photonic nonlinear compute units | No | Reported |
| Microsoft Research (Cambridge) Corporate lab Research | UK | Analog Iterative Machine — analog-optical fixed-point / optimization computer AIM prototypes | Optical optimization solver results on QUMO/portfolio problems | No | Verified |
Processing-in-memory & analog compute-in-memory
| Organisation | Region | Approach | Result or claim | Learns live | Verification |
|---|---|---|---|---|---|
| Samsung Electronics Corporate Standardization -> commercialization | South Korea | HBM-PIM (Aquabolt-XL), LPDDR-PIM, CXL-PNM; JEDEC LPDDR6-PIM standardization with SK hynix LPDDR6-PIM standard track (2026 target) | Claimed ~2x performance and ~70% power reduction vs conventional memory paths for target AI ops | No | Reported |
| SK hynix Corporate Prototype -> commercial | South Korea | GDDR6-AiM; AiMX LLM accelerator card; CuD (compute-using-DRAM); custom HBM CES 2026 lineup: PIM, AiMX, CuD, cHBM, CXL CMM | 16x DRAM-op speedup class results for GDDR6-AiM; LLM offload accelerator prototypes | No | Reported |
| EnCharge AI Startup Commercial ramp | USA | Switched-capacitor analog in-memory computing EN100 accelerator | ~200 TOPS-class at very high TOPS/W for edge/client inference | No | Reported |
| Mythic Startup Commercial | USA | Analog flash compute-in-memory M1076 AMP | Analog CIM inference at low power | No | Reported |
| Rain AI Startup Development | USA | Digital compute-in-memory tiles (roots in analog / equilibrium learning research) CIM chiplet designs | Energy-per-MAC claims for CIM tiles | No (research roots in EqProp) | Reported |
| Axelera AI Startup Commercial | Netherlands | Digital SRAM in-memory computing Metis AIPU; EuroHPC Titania efficiency award | High TOPS/W edge inference | No | Reported |
| Witmem (Zhicun) Startup Commercial (edge) | China | Analog flash CIM WTM2101 | Ultra-low-power always-on audio/health inference | No | Reported |
| Houmo.ai Startup Commercial | China | PIM for automotive / LLM edge H30 / H50 lines | PIM NPUs for in-cabin LLMs | No | Reported |
| TetraMem Startup Prototype | USA | Multi-level RRAM analog CIM MX100-class demos | Multi-bit memristor inference accuracy results (Nature-family papers with academic partners) | No | Reported |
| Tsinghua University + Huawei + ByteDance Academic + Industry Prototype silicon | China | Hybrid in-memory computing, 28 nm Recommendation-system inference chip | Reported 66x QPS and 181x QPS/W on recommendation workloads (1-2 orders of magnitude) | No | Reported; industrial co-authors, not independently replicated |
Model classes: energy-based & learn-at-inference
| Organisation | Region | Approach | Result or claim | Learns live | Verification |
|---|---|---|---|---|---|
| Charlot Lab / Institute for Physical AI @ BMI (EFA + Ferric) Nonprofit institute lab Whitepaper + measured nano-to-small suite | USA (Texas) | Energy First Architecture: one learned scalar energy over a sparse-positive monosemantic latent; Hebbian fast-weight memory written at inference; dendritic continual gate; JEPA world model + MPPI; flow-matching actuation + contrastive energy verifier; contraction-metric certificates. Ferric: pure-Rust cross-fabric GPU stack (WebGPU/Metal/datacenter) EFA whitepaper v1 + open repo + validation ledger; runs in-browser on Ferric | Descent-trained EBT 22->100% with thinking K=1->6; MPPI planning 39->69% on same value net; generate-then-check verify 99.6%; 30.4% certified contraction region with 100% empirical convergence; Lotka-Volterra recovered from real 1900-1920 lynx-hare data; pre-registered claims falsified and corrections documented | Yes (definitional: gradient-free Hebbian writes + gate at inference) | Self-published (open, reproducible artifacts) |
| AMI Labs (Yann LeCun) Startup Fundamental research phase (multi-year pre-product, stated openly) | France | JEPA world models as the post-LLM paradigm: predict abstract representations of future states; learn from physical reality, not text; LeJEPA linear-identifiability proof (May 2026) Founded after LeCun left Meta (Dec 2025, 12 years, FAIR founder); CEO Alexandre LeBrun (Nabla); targets robotics, healthcare, industrial automation; first partner Nabla | The paradigm's second billion-dollar lineage-carrier event in one year (after Unconventional AI): a Turing laureate leaving the incumbent to bet against LLM scaling, capitalized before product | Expected (world-model premise; JEPA is EFA's cited lineage) | Verified |
| VERSES AI (Friston) Public company Product beta | Canada / USA / UK | Active inference; Bayesian structure learning (AXIOM); Genius platform AXIOM digital-brain agent | Gameworld 10K vs DreamerV3: ~60% higher score (77 vs 48), 7.6x sample efficiency, 39x faster runtime, 400x smaller (0.95M vs 420M params); third-party validated, company-designed benchmark | Yes (single-pass Bayesian updates; grows/prunes online) | Reported (validated by Soothsayer Analytics) |
| Gladstone, Du et al. (UIUC / UVA / Harvard ecosystem) Academic Research | USA | Energy-Based Transformers: verify-then-descend prediction; System-2 as energy minimization EBT paper + code (arXiv 2507.02092) | Up to 35% faster pretraining scaling than Transformer++ across data/params/FLOPs/depth; +29% inference-time thinking gains; beats DiT on denoising with 99% fewer forward passes | No (test-time compute, frozen weights) | Verified (paper; replication ongoing) |
| Microsoft Research Asia (BitNet) Corporate lab Open models | China | Native ternary LLMs (BitNet b1.58); bitnet.cpp runtime BitNet b1.58 2B4T open model | Ternary weights {-1,0,+1} retain quality at scale; the ternary alphabet used by settling / CIM substrates | No (training-time ternarization) | Verified |
| Google (Titans / test-time memory line) Corporate Research | USA / UK | Surprise-gated neural memory written at inference (Titans); TTT lineage Titans architecture | Long-context memory via inference-time weight updates | Yes (fast weights at inference) | Verified (paper) |
| Stanford / Meta (Sun et al., TTT) Academic + corporate Research | USA | Test-Time Training layers (hidden state = weights updated by gradient at inference) TTT-Linear / TTT-MLP | TTT layers competitive with strong Transformers/Mamba at long context | Yes | Verified |
| Yang et al. (MIT ecosystem) — DeltaNet Academic Research | USA | Delta-rule fast-weight sequence models (Gated DeltaNet) DeltaNet / Gated DeltaNet | Hardware-efficient delta-rule attention alternatives; adopted into EFA's memory recipe | Yes (delta-rule writes) | Verified |
| JKU Linz (Hochreiter) / NXAI Academic + startup Research + startup | Austria | Modern Hopfield networks; xLSTM Hopfield-is-attention line; xLSTM-7B | Exponential-capacity associative memory; attention shown to be a Hopfield update | Partial | Verified |
| Krotov (IBM) + Hopfield lineage Academic / corporate lab Research | USA | Dense associative memory; Energy Transformer Energy Transformer | Transformer block reinterpreted as a single energy descent | Partial | Verified |
| Mila (Bengio, Scellier) — Equilibrium Propagation Academic Research | Canada / France | Equilibrium propagation: settle, nudge, settle; local weight updates EqProp theory + scaling papers | Backprop-equivalent gradients from two relaxations; basis for self-learning physical networks | Yes (local learning; the algorithm settling hardware needs) | Verified |
| UPenn (Dillavou, Liu, Durian) Academic Lab demos | USA | Self-learning nonlinear resistive networks (physical EqProp, no processor) Transistor-network learning machines | Physical circuits that learn tasks with local rules, no digital processor in the loop | Yes (physics does the update) | Verified |
| Cornell (McMahon) Academic Research | USA | Physics-aware training; deep physical neural networks PNN demonstrations (optical/mechanical/electronic) | Arbitrary physical systems trained as neural networks | Partial | Verified |
| Liquid AI Startup Commercial | USA | Liquid / continuous-time networks; LFM2 edge foundation models LFM2 (deployed on Klere's ternary-fabric among others) | Edge-first foundation models from continuous-time dynamics lineage | Partial (adaptive dynamics, not weight writes) | Reported |
| Pathway (BDH — 'The Dragon Hatchling') Startup research Research | Poland / USA | Brain-like sparse-positive scale-free architecture (BDH) BDH paper (2025) — lineage for EFA's latent | Sparse-positive activations bridging transformers and brain-like local rules | Partial | Reported |
| Zyphra (Millidge et al.) Startup Research + product | USA | Predictive coding theory + efficient hybrid sequence models PC theory papers; Zamba hybrids | Predictive coding as approximate backprop with local updates | Partial | Reported |
| Sakana AI Startup Research + product | Japan | Nature-inspired methods; Continuous Thought Machines CTM (2025) | Neural timing / synchronization as computation | Partial (internal temporal dynamics) | Reported |
Software abstraction & portability layer
| Organisation | Region | Approach | Result or claim | Learns live | Verification |
|---|---|---|---|---|---|
| Modular (acquired by Qualcomm) Startup -> acquired Acquired by QUALCOMM for ~$3.9B all-stock (announced Jun 24, closed Jul 29, 2026) - the first multi-billion exit for the make-hardware-fungible thesis; total raised $380M at $1.6B (Sep 2025) | USA | Hardware-agnostic AI stack: Mojo language (Pythonic syntax, C/CUDA-class perf, retargetable kernels), MAX inference engine (OpenAI-compatible serving across NVIDIA/AMD/Apple GPUs + Intel/AMD/ARM CPUs), Mammoth orchestration; founded by Chris Lattner (LLVM, Clang, Swift, MLIR) Mojo 1.0 beta (May 2026), compiler open-source committed end-2026; MAX claims ~2x vLLM across hardware; Meta a customer; BentoML acquired Feb 2026 | A hardware vendor paid ~$4B for credibly-neutral portability software; Lattner = the IR-layer lineage carrier pattern. Watch: does neutrality survive ownership by a silicon vendor? | n/a | Verified |
| ZLUDA Open-source project Active; post-commercial-funding 'back to the roots' hobby status after AMD (2022-24) and a later backer lapsed | Poland / global | CUDA-on-non-NVIDIA translation layer; runs unmodified CUDA binaries via ROCm v6 (Jun 2026): CUDA 13.1 compatibility, full llama.cpp, ROCm7, Windows tooling | Proof translation works; legal ambiguity vs NVIDIA EULA unresolved; community consensus: Vulkan/native paths have matured enough that the CUDA moat matters less for ML specifically | n/a | Verified |
| OpenAI Triton + Google OpenXLA / StableHLO / IREE + MLIR Corporate open-source Corporate-funded open source | USA | Triton: Python kernel DSL, now PyTorch's de facto portable kernel layer with NVIDIA/AMD/Intel backends. MLIR: the extensible compiler IR (Lattner-originated at Google) underlying nearly every stack here; StableHLO/IREE lower one graph to CUDA/ROCm/Vulkan/Metal/CPU The 'three kingdoms' of the AI compiler wars (with Mojo/MAX); MLIR dialects are the neutral ground where a NEW paradigm's ops could land | STRATEGIC: every current IR's primitives are tensors/kernels/streams - a settling fabric, TSU, or Ising machine has no representation. The cross-paradigm dialect is unclaimed territory | n/a | Verified |
| UXL Foundation (oneAPI / SYCL) Consortium Active standardization; adoption lags CUDA | Global (Linux Foundation) | Intel-seeded oneAPI/SYCL open standard; members incl. Intel, Google, Arm, Qualcomm, Samsung, Fujitsu; academic AdaptiveCpp (Heidelberg) Cross-vendor C++ heterogeneous programming | The explicit anti-CUDA alliance of the second-source vendors; historical caution: OpenCL died of committee pace | n/a | Verified |
| Khronos Vulkan compute + WebGPU ecosystem Standards + open-source Mature and accelerating | Global | Vulkan/SPIR-V as vendor-neutral GPU compute; WebGPU as the browser-universal layer (MLC-LLM/WebLLM, ONNX Runtime Web; Ferric builds here) llama.cpp Vulkan backend now runs LLMs on essentially any GPU (AMD/Intel/NVIDIA/mobile); WebGPU ships in all major browsers | The quiet winner: community consensus (2026) is that mature Vulkan/native paths already erode the CUDA moat for inference. WebGPU is the most universal deployment substrate that exists - which is why Ferric targets it | n/a | Verified |
| ggml / llama.cpp ecosystem (+ bitnet.cpp) Open-source Dominant in practice at the edge | Global (origin: Bulgaria/community) | Minimal quantized-inference runtime with CPU/Metal/CUDA/Vulkan/SYCL backends; the de facto universal edge AI runtime; Microsoft's bitnet.cpp (ternary) builds on it; Klere's ternary-fabric is adjacent Runs frontier open models on laptops, phones, Raspberry Pi | Arguably the most SUCCESSFUL hardware-irrelevance project in production - achieved by radical simplicity + quantization, not by grand IR unification | n/a | Verified |
| Apache TVM / OctoAI -> NVIDIA; tinygrad Open-source / startup TVM absorbed; tinygrad active | USA | TVM: pioneering ML compiler for any backend; its commercial home OctoAI was ACQUIRED BY NVIDIA (2024). tinygrad (tiny corp, G. Hotz): minimal universal accelerator abstraction, 'commoditize the petaflop' TVM lives on in MLC; tinygrad ships AMD-first boxes | CAUTIONARY: the incumbent BOUGHT a leading portability layer - neutrality is fragile and acquisition is a containment strategy. CC0/consortium governance is the defense | n/a | Verified |
| Huawei CANN + torch_npu (open-sourced) Corporate Aggressive national adoption push; usability complaints persist | China | CANN open-sourced Aug 2025 as the CUDA counter ('CUDA is Windows, CANN aims to be Linux'); torch_npu makes standard PyTorch run on Ascend - killing the biggest switching cost; Atlas 950 SuperPoD (8,192 NPUs) shown globally at MWC 2026 DeepSeek models ship DAY-ONE optimized for Ascend/Cambricon/Hygon + CANN (Sep 2025, Jan 2026); domestic chips added to state procurement lists | The Zhipu pattern at the software layer: open what the incumbent closes, subsidize adoption, capture a captive developer generation | n/a | Verified |
| China open-ecosystem campaign (Alibaba stack, Moore Threads MUSA, BAAI FlagOS/FlagGems, national unified programming model) Corporate + state + institute Building | China | Alibaba open-sourced its AI stack targeting CUDA (Jul 2026); Moore Threads' MUSA (CUDA-like + porting tools); BAAI's Flag-series open system software for diverse domestic chips [verify details]; reported movement toward a state-coordinated unified programming model so one codebase runs on any domestic accelerator Coordinated multi-vendor sovereignty play | Portability as industrial policy. NOTE: China's substrate portfolio (photonic, neuromorphic, memristor, NPU) makes it the actor that NEEDS cross-paradigm lowering most - the likeliest first home of a beyond-kernel unified IR | n/a | Reported |
| NIR (Neuromorphic Intermediate Representation) + Intel Lava Academic consortium + corporate open-source Adopted across the neuromorphic community | EU / USA | NIR: a graph exchange format that runs one spiking model across Loihi 2, SpiNNaker2, Xylo, Speck, and SNN simulators - the ONNX of neuromorphics (Nature Comms lineage, 2024). Lava: Intel's open framework for neuromorphic + conventional targets One model definition, many neuromorphic substrates - proof the cross-paradigm pattern works when primitives match the physics (spikes/state, not kernels) | THE TEMPLATE: the only shipping portability layer whose primitives are not tensors-on-clocks. A relaxation/sampling analogue (settle, sample, local-write, energy-budget) is the unbuilt missing middle - flowg/Joule (Klere) and Ferric are the nearest existing artifacts | n/a | Verified |
The graveyard: structural lessons
Kept deliberately. Every earlier wave of alternative computing failed for one of a small number of structural reasons, and those reasons are more instructive than the successes.
| Organisation | Region | Approach | Result or claim | Learns live | Verification |
|---|---|---|---|---|---|
| Untether AI Startup (wound down) Shut down Jun 2025; engineering team to AMD; products did not transfer | Canada | At-memory digital inference accelerator speedAI / tsunAImi products - discontinued | LESSON: fought on the incumbent's own scoreboard (dense inference throughput) where CUDA + capex compound; no software moat survived | No | Verified (shutdown) |
| Graphcore Startup (acquired) Sold to SoftBank ~$500-600M (2024), below the $742M raised from a $2.8B peak; 2022: $2.7M revenue vs $204.6M loss; co-founder exited 2025; now SoftBank subsidiary ($457M injection 2026, Bengaluru campus) | UK | IPU - architected explicitly NOT to look like a GPU IPU generations + Poplar stack | LESSON: novel architecture, incumbent's benchmark - it competed on GPU workloads against the CUDA ecosystem; differentiation in silicon without differentiation in scoreboard | No | Verified |
| Mythic (2022 episode) Startup (recapitalized) Recovered; listed above as active | USA | Analog flash CIM - ran out of cash 2022, revived smaller M1076 | LESSON: analog calibration/toolchain costs and long design-in cycles nearly killed a working product; edge sockets pay slowly | No | Verified |
| Lightmatter (compute era) Startup (pivoted) Thriving - as an interconnect company | USA | Photonic COMPUTE (Envise) largely shelved for photonic INTERCONNECT (Passage) Envise -> Passage | LESSON: the market repriced photonics from 'replace the GPU' to 'feed the GPU'; adjacency was survival. Watch whether Neurophos/OLIX escape the same gravity | No | Reported |
| Wave Computing Startup (bankrupt 2020, pre-map) Chapter 11 (2020); emerged as MIPS licensor | USA | Dataflow processing units DPU line | LESSON: pre-history of this map - dataflow's promise died on software maturity and customer risk-aversion, not physics | No | Verified |
National programmes
Where the state money is.
Public commitments that shape which substrates get built. Figures are recorded as published, and a letter of intent is marked as a letter of intent rather than promoted to an award, which is the most common way these numbers get overstated.
| Region | Programme | Relevant scope | Public figure | Year |
|---|---|---|---|---|
| USA | CHIPS R&D / Dept. of Commerce | First thermodynamic-computing support: letter of intent with Extropic to scale probabilistic computing onshore | $75M LOI [LOI, not an award] | 2026 |
| USA | CHIPS R&D — GlobalFoundries silicon photonics LOI | Silicon photonics, optical materials, near/co-packaged optics for AI and HPC interconnect | $300M LOI [LOI, not an award] | 2026 |
| USA | DARPA / ONR / NSF / SRC programs | p-bits, Ising machines, unconventional & physics-based computing grants across UCSB, Purdue, Cornell, UPenn etc. | Not aggregated publicly [verify] | ongoing |
| China | 15th Five-Year Plan (adopted Mar 2026) | Brain-computer interfaces and brain-inspired technology named future strategic industries alongside quantum and 6G | Plan-level commitment (no single figure) | 2026 |
| China | MIIT + NDRC + CAS BCI implementation plan | Roadmap targeting core BCI/brain-tech breakthroughs and 2-3 industrial clusters by 2027 | Plan-level | 2025 |
| China | Big Fund III (National IC Fund phase 3) | General semiconductor fund; enables photonic pilot fabs and advanced packaging that alternative substrates ride on | ~$47.5B (RMB 344B) | 2024 |
| China | Photonic pilot fabs (Wuxi / SJTU; CHIPX-Turing Quantum; Shanghai optical computing lab) | Domestic photonic chip production lines; framed by state media as strategic answer to export controls | State-backed; figures undisclosed [verify] | 2025-26 |
| Japan | NEDO + corporate programs; IOWN Global Forum (NTT-led) | Quantum-inspired annealing commercialization; photonics-electronics convergence roadmap | Multi-company consortium | ongoing |
| South Korea | JEDEC LPDDR6-PIM standardization (Samsung + SK hynix); K-semiconductor strategy | Industry-led PIM standardization for on-device AI; national semiconductor incentives | Industry-funded; national incentives separate | 2024-26 |
| South Korea | AI national champions program | $390M for five domestic foundation-model champions (adjacent: creates demand for efficient inference) | $390M | 2026 |
| EU | Human Brain Project (completed 2023) -> EBRAINS research infrastructure | Decade-scale neuromorphic + brain-simulation investment; SpiNNaker and BrainScaleS platforms | ~EUR 607M over 10 years | 2013-2023 |
| Gulf (Saudi / UAE / Qatar) | HUMAIN (PIF), G42 + MGX + Stargate UAE, Qai | Sovereign GPU-paradigm buildout at extreme scale: HUMAIN ~2,200 MW planned, multi-supplier (NVIDIA, AMD, AWS, Qualcomm, xAI); Stargate UAE 1 GW first phase (~400k NVIDIA chips reported), 5 GW campus target; $31-52B UAE data center in France; 35k Blackwell-class export approvals each (Nov 2025) | Tens of billions committed (PIF ~$1T; MGX ~$100B target) | 2025-26 |
| India | India Semiconductor Mission 2.0 (Semicon 2.0, cabinet-approved Jul 15, 2026) | RS 1.27 lakh crore (~$15B) next phase: equipment/materials self-reliance, indigenous IP, advanced-node roadmap; ~RS 1.6 lakh crore project pipeline across 10-12 approved fabs/OSATs (Tata-PSMC Dholera 28-110nm, first production end-2026; Micron & Kaynes ATMP operational; Tata-ASML front-end agreement May 2026) | ~$15B (phase 2) + phase-1 RS 76,000 crore | 2026 |
| Global (metrology) | MLCommons Power working group (MLPerf Power) | The existing industry standard for AI energy measurement: 20+ orgs (Meta, Google, NVIDIA, Intel, Fujitsu, Infineon), HPCA 2025 methodology paper, 1,841 reproducible measurements across 60 systems from microwatts to megawatts; SPEC-approved analyzers required at the edge | Consortium-funded | 2024-26 |
| EU | EU AI Act - energy transparency for GPAI models (Art. 53, Annexes XI-XII) | Providers of general-purpose AI models MUST document known or estimated energy consumption; AI Office can demand it without notice; fines up to EUR 15M or 3% of global turnover; grace period for pre-Aug-2025 models to Aug 2, 2027; 2026 consultation explicitly supports an appliance-style AI energy label | Regulatory mandate (not a fund) | 2025-27 |
| EU | EIC Pathfinder / Chips JU | Unconventional & in-memory computing calls; Axelera EuroHPC award | Program-level [verify] | ongoing |
| UK | Neuroware Innovation & Knowledge Centre (UCL-led) | UK's first IKC for neuromorphic hardware; UCL + Imperial, King's, Cambridge, Oxford, Manchester, Strathclyde, Sheffield, NPL; commercialization focus | GBP 12.8M (EPSRC + Innovate UK) | 2025 |
| UK | UK Multidisciplinary Centre for Neuromorphic Computing (EPSRC) | Fundamental research: novel materials, photonic hardware, stem-cell-derived human neurons, low-power algorithms; explicit 20 W-brain framing | GBP 4.48M (80% of GBP 5.6M FEC), 4 years | 2025-26 |
| UK | ARIA Scaling Compute programme | Explicit >=1000x AI energy-reduction target via unconventional compute (led by S. Bramhavar) | ~GBP 42M [verify] | 2024- |